Companies Home Search Profile
TrainingHub TrainingHub

Video Processing with FPGA

Focused View

Digitronix Nepal

4:14:49

24 View
  • 001 Section-1HLS-Overview-Powerpoint.pdf
  • 001 VIVADO High Level Synthesis [HLS] Overview.mp4
    11:29
  • 002 Overview of Xilinx VIVADO , IP and Zynq FPGA Architecture.mp4
    11:52
  • 003 AXI Protocol Overview.mp4
    17:09
  • 003 AXI-Protocols-Overview-July9-2020.pdf
  • 004 TPG Overview.mp4
    16:33
  • 005 Lab 1 Part I_ TPG Project Development LAB on VIVADO.mp4
    19:38
  • 005 tpg-Complete-VIVADO-Project.xpr.zip
  • 005 tpg-complete-vivado-project-Nov7.pdf
  • 006 Lab 1 Part II_ TPG Development [SDK Configuration with Zynq PS].mp4
    06:41
  • 006 main.zip
  • 007 Demo_ TPG Implementation on ZedBoard FPGA.mp4
    04:57
  • 008 TPG and VDMA Overview.mp4
    13:54
  • 009 Lab 2 Part I_ TPG & VDMA- VIVADO IP Block Design.mp4
    07:18
  • 009 tpg-and-vdma-block-design.pdf
  • 009 tpg-with-vdma-complete-project.xpr.zip
  • 010 Lab 2 Part II_ TPG & VDMA- SDK Application Development.mp4
    04:48
  • 010 tpg-vdma-lab-sources-vivado-sdk-udemy.zip
  • 011 Demo_ TPG & VDMA Project Implementation on ZedBoard.mp4
    02:29
  • 012 Sobel Edge Detection-HLS & OpenCV Algorithm.mp4
    16:47
  • 012 sobel-edge-detect-all-sources-march25-with-readme.zip
  • 013 Lab 1 Sobel IP Design on VIVADO HLS.mp4
    19:16
  • 013 sobel-edge-detection-HLS-complete-project.zip
  • 014 Lab 2 VIVADO IP integration of Sobel Edge IP on Streaming Mode.mp4
    23:09
  • 014 Workbook-Digilent-ZYBO-Video-Workshop-2.pdf
  • 014 Zybo-Constraint.zip
  • 014 block-design-sobel-tested-zybo-720p-march25.pdf
  • 014 sobel-edge-detect-all-HLS-sources-march25-with-readme.zip
  • 014 sobel-zybo-tested-march25-VivadoE8-2.xpr.zip
  • 014 vivado-library-of-digilent-ip.zip
  • 015 Sobel Edge Demonstration on Zybo FPGA.mp4
    02:30
  • 016 Sobel Edge Detection with Zybo Z7-10-Lab Session.mp4
    06:12
  • 016 zybo-z7-10-hdmi-sobel-IP.xpr.zip
  • 017 Sobel Edge Detection with Zybo Z7-10 [Demo].mp4
    01:19
  • 018 Sobel Edge Detection streaming design Zybo Z7-10.html
  • 018 Zybo-Z7-10-Sobel-Passthrough-V2-march29-2020.xpr.zip
  • 019 Sobel Edge Detection with ZedBoard and FMC HDMI.mp4
    04:38
  • 019 ZeddBoard-FMC-HDMI-Sobel-Block-Design.pdf
  • 020 Histogram Equalize Overview.mp4
    09:13
  • 020 histogram-equalize-hls.zip
  • 021 Fast Corner Detection Algorithm Overview.mp4
    08:32
  • 022 Lab 31_ Fast Corner Algorithm HLS Synthesis, C Simulation & Implementation.mp4
    18:17
  • 022 Lab-fast-corner.zip
  • 023 Harrish Corner Overview and Lab Intro.mp4
    07:52
  • 023 Harrish-Corner-Detection-HLS-Sources.zip
  • 023 harris-corner-hls-project-E8-2.zip
  • 024 HLS-UseModel-Usage-Doc.pdf
  • 024 Harris-Corner-Detection-in-Vivado-HLS-using-xfOpenCV-V3.pdf
  • 024 Porting xfOpenCV Harrish Corner into HLS.html
  • 025 Lab_ Video Mixer feature implementation on Zybo Z7-10 board.html
  • 025 Video-Mixer-SDK-Source.zip
  • 025 Xilinx-Zynq-Video-Mixer-Tutorial-LogicTronix-june30-2020.pdf
  • 025 video-mixer-vivado-block-design.pdf
  • 026 2TPG-ZedBoard-Tcl-Block-Design-VIVADO-Vitis-E92.zip
  • 026 Lab_ 2 TPG and Video Mixer Design with ZedBoard FPGA.html
  • 026 Video-Mixer-2TPG-Sources-Tcl-SDK-vivadoE9-1.zip
  • 027 Lab_ Video Mixer, 2 TPG and HDMI implementation on ZedBoard FPGA.mp4
    20:16
  • 028 What Next_.html
  • 029 Reference Links.html
    •

    Description

    Implementing different Computer Vision Algorithm on Xilinx Zynq FPGA with VIVADO High Level Synthesis & SDK

    What You'll Learn?

    • Implement different Computer Vision algorithm for Video Processing
    • Creating IP from the VIVADO High Level Synthesis
    • IP integration and configuration with Xilinx VIVADO
    • Xilinx SDK Application Development
    • Migrating the OpenCV algorithm on XfOpenCV
    • Simulating & Generating xfOpenCV codes in the VIVADO HLS
    • Integrating TPG, VDMA and Writing application for this blocks
    • Vitis HLS and OpenCV installation Session for 2020.2 or later

    Who is this for?

  • Electrical Engineering Enthusiast
  • Computer Science Enthusiast
  • FPGA Design Professional
  • Enthusiast of FPGA Design

    • What You Need to Know?

  • Basics of FPGA Design
  • High Level Synthesis Basics
  • PC with installed VIVADO, HLS and SDK [we will also show the steps for installation]

    • More details

    Description

    This Course is on implementing different Video Processing algorithm on FPGA. We implement the algorithm on High Level Synthesis [HLS], simulate it with the image input, generate & export IP from the HLS. The HLS IP is integrated with the necessary video processing pipeline [block design] and implemented on the FPGA Device.

    We have "Implemented Sobel Edge Detection, Dilation, Histogram Equalize, Fast Corner like algorithm" on HLS and then FPGA. For the debugging the algorithm on the FPGA, we have initialized the Test Pattern Generator [TPG] IP and Video DMA [VDMA] for processing the image streams on the DDR with the Processing System involvement.

    After Completing this course you will be able to:

    1. Utilized the HLS Video Processing Library and Implement as well as Simulate different OpenCV Algorithm on HLS

    2. Integrating the HLS IP with Video Processing Pipeline with TPG and VDMA and Implementing on the FPGA Device.

    3. Implementing the XfOpenCV [SDSoC] Library on HLS for Computer Vision

    4. Migrating the OpenCV algorithm into XfOpenCV

    Who this course is for:

    • Electrical Engineering Enthusiast
    • Computer Science Enthusiast
    • FPGA Design Professional
    • Enthusiast of FPGA Design

    User Reviews
    Rating
    0
    0
    0
    0
    0
    average 0
    Total votes0
    Focused display
    Category

    Artificial Intelligence

    FPGA

    Digitronix Nepal
    Digitronix Nepal
    Instructor's Courses
    Digitronix Nepal is an FPGA Design Company serving global customers since 2013. As of the initiative of "Democratizing FPGA Education all over the World", Digitronix Nepal has partnered with LogicTronix [FPGA Design and Machine Learning Company] for creating online learning courses and tutorials on "FPGA, VHDL/Verilog, Computer Vision & Video Processing, High Level Synthesis (HLS), MATLAB/System Generator, Machine Learning Acceleratio, SDAccel, SDSoC, Pynq Development, etc."Digitronix Nepal believes that with the "Ultra Low Cost and FREE Courses" on FPGA Design, enthusiast from any country can learn and explore on the Field of FPGA Design and grab the global opportunities on FPGA Design, ASIC/VLSI Design and Machine Learning Acceleration.
    Udemy
    Udemy
    View courses Udemy
    Students take courses primarily to improve job-related skills.Some courses generate credit toward technical certification. Udemy has made a special effort to attract corporate trainers seeking to create coursework for employees of their company.
    • language english
    • Training sessions 23
    • duration 4:14:49
    • Release Date 2024/04/20

    Courses related to Artificial Intelligence

    Meet the Expert Yves Hilpisch on Artificial Intelligence in Finance
    O'ReillyMeet the Expert Yves Hilpisch on Artificial Intelligence in Finance
    1:04:37
    10/31/2023
    Machine Learning Bookcamp
    Manning PublicationsMachine Learning Bookcamp
    8:59:20
    10/23/2023
    Gen AI - LLM RAG Two in One - LangChain + LlamaIndex
    Udemy
    Gen AI - LLM RAG Two in One - LangChain + LlamaIndex
    9:13:10
    03/04/2025

    Courses related to FPGA

    Altera FPGAs: Learning Through Labs using VHDL
    Udemy Jordan Christman
    Jordan Christman
    Altera FPGAs: Learning Through Labs using VHDL
    1:47:14
    12/10/2022
    Subtitle
    FPGAs Development with Xilinx Vivado tool & Pcie full project
    SkillShareFPGAs Development with Xilinx Vivado tool & Pcie full project
    7:54:45
    English subtitles
    01/14/2024
    Subtitle
    Introduction to VHDL for FPGA and ASIC design
    Udemy Scott Dickson
    Scott Dickson
    Introduction to VHDL for FPGA and ASIC design
    7:08:20
    English subtitles
    03/25/2024