Verilog Lint essentials for RTL Design Engineer

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Kumar Khandagle

3:10:32

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1 - Day 1 Lint Basics

1 -Agenda.mp4

01:33

2 -Analysis Types.mp4

05:50

3 -Lint Usage.mp4

02:31

4 -Typical format of Lint violation P1.mp4

03:08

5 -Typical format of Lint violation P2.mp4

03:14

6 -Typical format of Lint violation P3.mp4

01:15

7 -Performing Lint with Verilator.mp4

04:15

8 -Performing Lint with Vivado 2024.1.mp4

08:44

2 - Day 2 Lint Rules P1

1 -Agenda.mp4

00:41

2 -Lint Rules Overview.mp4

01:31

3 -Reset rules P1.mp4

02:31

4 -Reset rules P2.mp4

06:17

5 -Reset rules P3.mp4

01:26

6 -Bad Code.mp4

02:14

7 -Good Code.mp4

01:41

8 -Clock rules P1.mp4

01:29

9 -Clock rules P2.mp4

05:18

10 -Bad Code.mp4

01:32

11 -Good Code.mp4

00:34

3 - Day 3 Lint Rules P2

1 -Agenda.mp4

00:16

2 -Assignment rules P1.mp4

01:57

3 -Assignment rules P2.mp4

05:48

4 -Assignment rules P3.mp4

01:29

5 -Assignment rules P4.mp4

02:52

6 -Assignment rules P5.mp4

02:08

7 -Assignment rules P6.mp4

02:48

8 -Assignment rules P7.mp4

02:14

9 -Bad Code.mp4

03:22

10 -Good Code.mp4

01:17

11 -Operations.mp4

00:55

12 -Bad Code.mp4

01:51

13 -Good Code.mp4

00:43

14 -Naming rules P1.mp4

01:07

15 -Naming rules P2.mp4

05:42

16 -Naming rules P3.mp4

01:54

17 -Naming rules P4.mp4

05:21

18 -Code.mp4

00:58

19 -Loop Rules P1.mp4

01:02

20 -Loop Rules P2.mp4

04:45

21 -Loop Rules P3.mp4

02:01

22 -While loop Good & Bad Code.mp4

02:03

23 -For loop Good & Bad Code.mp4

01:12

4 - Day 4 Lint Rules P3

1 -Agenda.mp4

00:13

2 -Function & Task rules P1.mp4

01:31

3 -Function & Task rules P2.mp4

05:04

4 -Function & Task rules P3.mp4

02:10

5 -Bad Code.mp4

01:50

6 -Good Code.mp4

01:13

7 -Case rules P1.mp4

00:56

8 -Case rules P2.mp4

04:07

9 -Case rules P3.mp4

02:07

10 -Case rules P4.mp4

02:01

11 -Bad Code.mp4

02:33

12 -Good Code.mp4

00:55

13 -Combinational logic rules P1.mp4

00:40

14 -Combinational logic rules P2.mp4

01:52

15 -Good & Bad Code.mp4

02:11

5 - Day 5 Lint Rules P4

1 -Agenda.mp4

00:31

2 -Structural Modeling rules P1.mp4

01:30

3 -Structural Modeling rules P2.mp4

04:48

4 -Structural Modeling rules P3.mp4

04:11

5 -Structural Modeling rules P4.mp4

05:58

6 -Bad Code.mp4

00:57

7 -Good Code.mp4

00:35

8 -Multiple Drivers P1.mp4

00:33

9 -Multiple Drivers P2.mp4

02:48

10 -Code Hygiene P1.mp4

01:54

11 -Code Hygiene P2.mp4

03:49

12 -Code Hygiene P3.mp4

02:16

13 -Code Hygiene P4.mp4

05:07

14 -Code Hygiene P5.mp4

02:51

15 -Bad Code.mp4

01:43

16 -Good Code.mp4

01:00

17 -Synthesis P1.mp4

01:15

18 -Synthesis P2.mp4

06:38

19 -Bad Code.mp4

02:06

20 -Good Code.mp4

01:10

Description

Step by Step Guide from Scratch

What You'll Learn?

Role of Lint in DUT analysis
Reset & Clock best practices
Naming Conventions & Assignment Operators best practices
Loop best practices
Case best practices
Function & Tasks best practices

Who is this for?

Anyone interested in becoming an RTL Design Engineer.

What You Need to Know?

Fundamentals of Digital Electronics and Verilog

More details

Description
We have two types of analysis for the DUT (Device Under Test). The first type is static analysis, where we examine the design without applying any stimulus. This involves analyzing the constructs and coding patterns to identify early bugs or applying mathematical models to check the correctness of the DUT. Examples of static analysis include linting and formal verification.
The second type is dynamic analysis, where we apply a set of stimuli to the DUT based on test cases and analyze the response to verify functionality.
Linting is crucial in Verilog design to ensure code quality and prevent errors. It enforces coding standards, detects bugs early, and checks for correct syntax and semantics. Using lint tools helps Verilog engineers maintain consistency across codebases, enhance readability, and preempt issues that might not affect simulation but could lead to unexpected results during synthesis.
A key advantage of linting in RTL (Register Transfer Level) design is its ability to detect incorrect usage of clocks, resets, modeling styles, loops, and control structures, which can lead to unsynthesizable designs. The difficulty with these bugs is that they are often hard to identify during debugging, as they are typically logical errors. Early detection of these issues saves designers significant time and effort.
Who this course is for:
Anyone interested in becoming an RTL Design Engineer.

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FPGA

Kumar Khandagle

Instructor's Courses

I am working as FPGA Developer Lead in India's Finest Financial Technology Firm for the development of a next-generation High-Frequency Trading platform on Xilinx Alveo FPGA Cards. Before Joining Fintech, I spent three years as a VLSI Trainer at Mumbai University, India, and one year as Research Scientist at the Prominent R&D Centre for Applied Electronic Research of India contributing to the development of Gradient Controller,64 Mhz Receiver on FPGA for Indigenous MRI Machine. During my free time, I love to develop Udemy Courses. I also collaborated with Larsen & Toubro Technology Services, Power International in the development of various FPGA based Systems such as Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS. My area of interest includes Front End VLSI Design, SoC, and Chip Verification.

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