UVM for Verification Part 1 : Fundamentals

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Kumar Khandagle

10:13:51

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1. How to use IDE

1. Series Intro.mp4

01:28

2. Agenda.mp4

00:35

3. Use this code for understanding IDEs.html

4. EDAplayground Link.html

5. Working with EDAP.mp4

07:52

6. Working with Vivado.mp4

05:21

7. Working with Questa.mp4

03:06

2. Reporting Mechanism

1. Agenda.mp4

00:55

2. Different Reporting Macros.mp4

06:26

3. Working with Reporting Macros.mp4

09:19

4. Code.html

5. Priniting Values of Variables without automation.mp4

02:30

6. Code.html

7. Working with Verbosity Level.mp4

10:02

8. Code.html

9. Working with Verbosity Level and ID.mp4

09:30

10. Code.html

11. Working with Individual Component.mp4

06:14

12. Code.html

13. Working with Hierarchy.mp4

06:17

14. Code.html

15. Other Reporting Macros.mp4

06:12

16. Code.html

17. Changing Severity of Macros.mp4

06:17

18. Code.html

19. Changing Associated Actions of Macros.mp4

06:57

20. Working with quit_count and UVM_ERROR.mp4

06:07

21. Code.html

22. Working with log file.mp4

06:28

23. Code.html

24. A11.html

25. A12.html

26. A13.html

27. A14.html

28. A15.html

3. Getting Started with Base Classes UVM_OBJECT

1. Agenda.mp4

01:29

2. Fundamentals P1.mp4

06:00

3. Fundamentals P2.mp4

00:54

4. Fundamentals P3.mp4

05:55

5. Target.mp4

00:31

6. Creating Class.mp4

02:33

7. Deriving class from UVM_OBJECT.mp4

10:14

8. Using Field Macros P1 INT cont.mp4

06:35

9. Code.html

10. Using Field Macros P1 INT.mp4

08:02

11. Code.html

12. Using Field Macros P2 ENUM, REAL.mp4

05:36

13. Code.html

14. Using Field Macros P3 OBJECT.mp4

06:05

15. Code.html

16. Using Field Macros P4 Arrays.mp4

09:04

17. Code.html

18. Copy and Clone Method.mp4

07:52

19. Code.html

20. Shallow Vs Deep Copy.mp4

07:31

21. Code.html

22. Copy and Clone Method.mp4

04:42

23. Code.html

24. Compare Method.mp4

04:17

25. Code.html

26. Create Method.mp4

03:21

27. Code.html

28. Factory Override new vs create method.mp4

10:32

29. Code.html

30. do_print Method.mp4

06:35

31. Code.html

32. convert2string method.mp4

04:54

33. Code.html

34. do_copy method.mp4

05:34

35. Code.html

36. do_compare.mp4

08:48

37. Building Transaction Class p.html

38. A21.html

39. A22.html

4. UVM_COMPONENT

1. Agenda.mp4

00:56

2. Understanding UVM_TREE.mp4

05:04

3. Creating UVM_COMPONENT class.mp4

10:37

4. Code.html

5. Creating UVM_TREE P1.mp4

11:42

6. Creating UVM_TREE P2.mp4

03:34

7. Code.html

8. Getting path of the component p.html

5. config_db

1. Agenda.mp4

00:26

2. Understanding typical format of config_db.mp4

12:01

3. Code.html

4. Demonstration P1.mp4

04:39

5. Demonstration P2.mp4

12:21

6. Demonstration P3.mp4

04:37

7. Demonstration P4.mp4

03:08

8. Used Case.mp4

09:14

9. Code.html

6. UVM_PHASES

1. Agenda.mp4

01:07

2. Fundamentals of Phases.mp4

01:50

3. Classification of Phases Methods Used.mp4

03:57

4. Classification of Phases Specific Purposes P1.mp4

02:20

5. Classification of Phases Specific Purposes P2.mp4

03:41

6. Classification of Phases Specific Purposes P3.mp4

01:38

7. Classification Summary.mp4

03:52

8. How we override phases.mp4

08:34

9. Code.html

10. Understanding execuction of build_phase in multiple components.mp4

12:13

11. Code.html

12. Understanding execution of connect_phase.mp4

04:10

13. Code.html

14. Execution of Multiple instance phases.mp4

04:16

15. Raising Objection.mp4

07:41

16. Code.html

17. How Time consuming phases works in Single Component.mp4

03:35

18. Code.html

19. Time Consuming phases in multiple components.mp4

06:52

20. Code.html

21. Timeout.mp4

05:58

22. Code.html

23. Drain Time Individual Component.mp4

05:39

24. Code.html

25. Drain Time Multiple Components.mp4

05:29

26. Code.html

27. Phase Debug.mp4

02:19

28. Phase Debug Switch.html

29. Objection Debug.mp4

02:37

30. Objection Debug Switch.html

31. A51.html

7. TLM

1. Agenda.mp4

01:03

2. Fundamentals.mp4

11:18

3. Blocking PUT Operation P1.mp4

13:00

4. Code.html

5. Adding IMP to Blocking PUT Operation.mp4

08:11

6. Code.html

7. Port to IMP.mp4

07:38

8. Code.html

9. PORT-PORT to IMP.mp4

09:14

10. Code.html

11. Port to Export-IMP.mp4

06:34

12. Code.html

13. Get Operation.mp4

08:06

14. Code.html

15. Transport Port.mp4

09:09

16. Code.html

17. Analysis Port.mp4

10:33

18. Code.html

19. A71.html

20. A72.html

8. Sequence

1. Agenda.mp4

00:39

2. Fundamentals.mp4

05:50

3. Creating Sequences.mp4

17:10

4. Code.html

5. Understanding Flow.mp4

11:20

6. Code.html

7. Sending Data to Sequencer.mp4

08:53

8. Code.html

9. Sending Data to Driver Method 2 P1.mp4

04:24

10. Sending Data to Driver Method 2 P2.mp4

03:09

11. Code.html

12. Multiple Sequence in Parallel.mp4

09:56

13. Code.html

14. Changing Arbitration Mechanism P1.mp4

06:31

15. Changing Arbitration Mechanism P2.mp4

06:34

16. Code.html

17. Ways to Hold access of Sequencer.mp4

04:11

18. Holding Access of Sequencer P1.mp4

09:05

19. Code.html

20. Holding access of Sequencer P2 Priority.mp4

02:44

21. Code.html

22. Holding access of Sequencer P3 Lock Method.mp4

04:05

23. Code.html

24. Holding access of Sequencer P4 Grab Method.html

25. Code.html

9. Projects Combinational Adder

1. Agenda.mp4

00:39

2. Summary of the Verification Environment.mp4

04:31

3. Verification of Combinational adder DUT.mp4

01:45

4. Transaction Class.mp4

03:54

5. Sequence Class.mp4

02:46

6. Driver Class.mp4

04:39

7. Monitor Class.mp4

03:27

8. Scoreboard Class.mp4

02:18

9. Agent Class.mp4

01:21

10. Environment Class.mp4

00:49

11. Test Class.mp4

01:05

12. Testbench Top.mp4

02:54

13. DUT + Interface.html

14. Testbench.html

15. A91.html

10. Projects Verification of Sequential Adder

1. Design + Interface.mp4

01:07

2. Transaction + Generator.mp4

01:38

3. Driver.mp4

02:13

4. Monitor + Scoreboard.mp4

02:03

5. Agent + ENV + TEST.mp4

00:25

6. Testbench Top.mp4

02:13

7. DUT + Interface.html

8. Testbench.html

9. A101.html

11. Next Course of UVM Series

1. UVM for Verification Part 2 Projects.html

Description

Step by Step Guide for building Verification Environment from Scratch

What You'll Learn?

Fundamentals of Universal Verification Methodology
Reporting Macros and associated actions
UVM Object and UVM Component
UVM Phases
TLM Communication
Sequences
UVM Debugging features
Building UVM Verification Environment from Scratch

Who is this for?

Anyone interested in Verification Engineer Role

More details

Description
Writing Verilog test benches is always fun after completing RTL Design. You can assure clients that the design will be bug-free in tested scenarios. As System complexity is growing day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability helping verification engineers quickly locate hidden bugs. The System Verilog lags structured approach whereas UVM works very hard on forming a general skeleton. The addition of the configuration database Shifts the way we used to work with the Verification Language in the past. Within a few years, verification engineers recognize the capabilities of UVM and adopted UVM as a defacto standard for the RTL Design verification. The UVM will have a long run in the Verification domain hence learning of UVM will help VLSI aspirants to pursue a career in this domain.
The course will discuss the fundamentals of the Universal Verification Methodology. This is a Lab-based course designed such that anyone without prior OOPS or system Verilog experience can immediately start writing UVM components such as Transaction, Generator, Sequencer, Driver, monitor, Scoreboard, Agent, Environment, Test. Numerous coding exercises, projects, and simple examples are used throughout the course to build strong foundations of the UVM.
Who this course is for:
Anyone interested in Verification Engineer Role

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I am working as FPGA Developer Lead in India's Finest Financial Technology Firm for the development of a next-generation High-Frequency Trading platform on Xilinx Alveo FPGA Cards. Before Joining Fintech, I spent three years as a VLSI Trainer at Mumbai University, India, and one year as Research Scientist at the Prominent R&D Centre for Applied Electronic Research of India contributing to the development of Gradient Controller,64 Mhz Receiver on FPGA for Indigenous MRI Machine. During my free time, I love to develop Udemy Courses. I also collaborated with Larsen & Toubro Technology Services, Power International in the development of various FPGA based Systems such as Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS. My area of interest includes Front End VLSI Design, SoC, and Chip Verification.

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