Simple AXI bus Design using Verilog HDL

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Surender R

1:03:48

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1 - Course Introduction

1 - Introduction.mp4

02:37

2 - AMBA introduction.mp4

01:38

3 - Comparision between AHB AXI APB.mp4

02:58

2 - AXI bus

4 - Introduction to AXI.mp4

01:22

5 - AXI channel Architecture of Readwrites.mp4

04:22

6 - AXI signals.mp4

01:13

7 - Handshaking signals.mp4

01:46

8 - Signal Diagram.mp4

05:09

9 - Write process Timing diagram.mp4

02:12

10 - Read process Timing diagram.mp4

02:12

11 - Dependencies between channel handshake signals.mp4

01:42

3 - Implementation of Simple AXI bus

12 - AXI state machine for write read.mp4

00:33

13 - AXI MasterSlave Block diagram and Writeread process.mp4

02:23

4 - Source code

14 - Design of AXI bus using verilog HDL write process.mp4

18:11

14 - axi-master-write.zip

14 - axi-slave-write.zip

15 - Design of AXI bus using verilog HDL Read process.mp4

11:58

15 - axi-master-read.zip

15 - axi-slave-read.zip

16 - AXI master slave.mp4

01:56

16 - axi-master.zip

16 - axi-slave.zip

17 - Test bench simulation.mp4

01:36

17 - design.zip

17 - testbench.zip

Description

AXI in easy understand

What You'll Learn?

Concept of AMBA bus protocol
Concept of AXI Bus
Design and implementation of AXI bus using Verilog HDL
Verification of AXI bus

Who is this for?

Intermediate level people who planning to going for job

What You Need to Know?

Verilog HDL

More details

Description
AMBA is an open standard for SoC design created by Arm to allow for high-performance, modular, and reusable designs that work right the first time while minimizing both power and silicon.
Â Â Â Â Â Â This course discusses the AMBA, which introduced the Advanced Extensible Interface (AXI) protocol.
Originally conceived for high-frequency systems, the AXI protocol was designed to meet the interface requirements for a wide range of components, while allowing for flexibility in how those components are interconnected. Suitable for high-frequency, low-latency designs, AXI remains backward compatible with the AHB and APB from the previous AMBA revision.
Understanding AXI will give you deep insight into how an SoC works while making you a versatile and well-rounded designer.

Â Â Â Â Â Â Â Recall that the AHB (Advanced High-Performance Bus) is a single-channel bus that multiple masters and slaves use to exchange information. A priority arbiter determines which master currently gets to use the bus, while a central decoder performs slave selection. Operations are performed in bursts that can take multiple bus cycles to complete. Every burst transfer consists of an address and control phase followed by a data phase.
Â Â Â Â Â Â AXI was designed with a similar philosophy but uses multiple, dedicated channels for reading and writing. AXI is burst-based like its predecessor and uses a similar address and control phase before data exchange. AXI also includes several new features including out-of-order transactions, unaligned data transfers, cache support signals, and a low-power interface.
Â Â Â Â You can refer to AMBA AXI Protocol v1.0 for a deeper look into the AXI.

Who this course is for:
Intermediate level people who planning to going for job

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Verilog HDL Programming

Surender R

Instructor's Courses

Having more than 10 years experience in IT having experience in verilog and system verilog & UVM and Python. I worked on different project covered more than 50 verilog modules. I have experience on FPGA boards, and xilinx Zynq FPGA boards (which having ARM processor in it). I am planning to do future courses on General Microprocessor design with our own Instruction Set Architecture (ISA).

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