RISC-V Interrupts & Platform Level Interrupt Controller

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Benix Samuel Vincent Theogaraj

2:05:07

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1. Introduction

1. Course Overview.mp4

02:43

2. Privilege Levels and Traps in RISC-V

1. Privilege Levels in RISC-V.mp4

02:16

2. Traps in RISC-V.mp4

11:03

3. Platform Level Interrupt Controller Specification

1. Need for PLIC Specification.mp4

02:43

2. Interrupt Flow in PLIC.mp4

03:08

3. Operational Block Diagram.mp4

03:31

4. PLIC Parameters Memory Map In FE310 SoC.mp4

11:33

4. Install tools, write simple assembly code, compile, link and generate ELF

1. Install OpenOCD and GNU Toolchain.mp4

10:09

2. Demo Compile, Load, Execute and Debug with OpenOCD and GDB.mp4

13:48

5. Section 5 Control and Status Registers

1. Introduction to & demonstration of accessing Control and Status Registers.mp4

13:20

6. Hands on with Hifive1-Rev Board

1. Introduction.mp4

04:07

2. Configure GPIO 21.mp4

08:22

3. Configure PLIC to allow GPIO 21 interrupt.mp4

07:15

4. Configure E31 core CSRs to enable machine and machine external interrupt.mp4

02:26

5. Test application to blink the blue LED and generate interrupt.mp4

28:43

Description

Write RISC-V assembly code to configure GPIO, PLIC and Core CSRs to generate GPIO interrupt and blink blue LED on board

What You'll Learn?

Understand privilege levels, traps and control and status registers in RISC-V
Platform Level Interrupt Controller Specification for RISC-V
Sample implementation of PLIC module on RISC-V based FE310 SoC
Writing assembly code, compiling, linking with GNU tools and debugging with OpenOCD and GDB
Demonstration of interrupt generation & handling in RISC-V assembly

Who is this for?

Embedded system developers and RISC-V enthusiasts

What You Need to Know?

Brief knowledge on any processor like interrupts, interrupt priority & interrupt handling would help

More details

Description
Interrupts in RISC-V are governed by standards and specification. Each RISC-V core's interrupt generation and handling process should be compliant to the specification.

This course discusses the following:
a. Privilege Levels in RISC-V
b. Traps in RISC-V
c. Platform Level Interrupt Controller (PLIC) Specification
d. Compares PLICÂ Implementation on FE310 SoC to Spec
e. Control and Status Registers (CSRs)
f. Instructions to read and write CSRs in RISC-V
g. Configuring GPIOÂ peripheral in FE310 SoC
h. Configuring PLICÂ to allow GPIOÂ interrupt
i. Configure MIE &Â MSTATUS CSRs on the coreÂ to enable machine mode interrupts and machine mode external interrupts
j. Installation of GNUÂ tools (compilers, OpenOCD)
k. Test application in assembly to blink blue LEDÂ on Hifive1-Rev B board.

Students who enrol would be taken through a journey starting from basics of what are interrupts, exceptions and traps in RISC-V, followed by PLIC standard discussing the parameters, how to configure those parameters on PLICÂ to generate interrupt and claiming and completing the interrupt handling process and finally on writing an test application to blink LED.

The major exercise and focus on this course is on writing RISC-V assembly code, assembling &Â linking with GNUÂ tools, generating ELF, and programming it on Hifive1-RevB board to blink blue LED on board.

Who this course is for:
Embedded system developers and RISC-V enthusiasts

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Embedded Systems

Benix Samuel Vincent Theogaraj

Instructor's Courses

My journey on embedded systems firmware & software started from Indian Institute of Technology, Madras with Analog Devices's Blackfin Digital Signal Processors and then got introduced to ARM and MIPS Processors during work at Cisco Systems and Samsung for real time operating systems development. My journey on RISC-V started three years ago as a RISC-V enthusiast and now developing embedded systems with RISC-V processors.

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