Peter Yo

I am a master of microelectronics, and have about 15 years of experience in chip design, verification, and the EDA industry. As an expert in formal verification techniques, I have created a unique formal verification methodology. Many of the theories I have presented have been accepted as technical standards by most formal verification practitioners. I have many years of practical experience in formal verification and have developed and implemented formal verification solutions for many large-scale projects in many leading chip companies.