FPGAs Development with Xilinx Vivado tool & Pcie full project
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7:54:45
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01 - intro.mp4
02:04
02 - 1-introduction.mp4
02:53
03 - 2-download-vivado.mp4
04:17
04 - 3-download-modelsim.mp4
03:58
05 - 4-open-new-project.mp4
05:00
06 - 5-open-existing-project.mp4
01:33
07 - 6-opening-example-project.mp4
06:18
08 - 7-adding-files-to-project.mp4
09:27
09 - 8-creating-block-design-adding-ip.mp4
16:25
10 - 9-ip-cores-and-opening-xilinx-ip-example-design.mp4
12:38
11 - 10-language-templates-primitive-cores.mp4
08:12
12 - 11-synthesis.mp4
08:24
13 - 12-implementation.mp4
03:22
14 - 13-constraints.mp4
12:05
15 - 14-constraints-wizard.mp4
05:28
16 - 15-language-templates-xdc.mp4
03:19
17 - 16-view-rtl-schematic.mp4
03:13
18 - 17-create-bitstream-file.mp4
04:53
19 - 18-load-bit-file-to-the-fpga.mp4
03:54
20 - 19-creating-bin-file-or-mcs-file-through-vivado.mp4
16:08
21 - 20-running-vivado-simulation.mp4
04:26
22 - 21-modelsim-configuration.mp4
07:56
23 - 22-running-and-using-modelsim-simulator.mp4
16:42
24 - 23-zynq7000-and-axi-intro.mp4
47:30
25 - 24-axi-memory-map-vs-axi-stream.mp4
18:37
26 - 25-export-hardware-creating-hdf-file.mp4
07:44
27 - 26-open-sdk-new-project.mp4
23:13
28 - 27-zynq7000-mcs-or-bin-files.mp4
14:12
29 - 28-creating-ila-in-vivado.mp4
23:58
30 - 29-run-the-ila.mp4
11:30
31 - 30-pcie-full-project-part1.mp4
44:30
32 - 31-pcie-full-project-part2.mp4
48:43
33 - 32-pcie-full-project-part3.mp4
39:50
34 - 33-pcie-full-project-part4.mp4
32:23
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- language english
- Training sessions 34
- duration 7:54:45
- English subtitles has
- Release Date 2024/01/29
