Companies Home Search Profile

Embedded System Design with Xilinx Zynq SoC and Vitis IDE

Focused View

Kumar Khandagle

9:17:38

22 View
  • 1. Downloading Setup Files.mp4
    03:57
  • 2. Choosing Installation Settings.mp4
    02:28
  • 3.1 xilinx (1).zip
  • 3. LIC File.html
  • 4. Adding License.mp4
    00:56
  • 5. Digilent Board files Download this before proceeding to the next Video.html
  • 1. Introduction P1.mp4
    08:45
  • 2. Introduction P2.mp4
    03:50
  • 3. Introduction P3.mp4
    06:42
  • 4. Fundamentals P1 Project Types.mp4
    03:42
  • 5. Fundamentals P2 Flow Navigator.mp4
    08:18
  • 6. Using TCL Script for Block Automation.mp4
    09:17
  • 1. Ways to access Peripherals from Zynq P1.mp4
    04:02
  • 2. Ways of accessing Peripherals from Zynq.mp4
    11:00
  • 3. Fundamentals of XIL Drivers P1.mp4
    04:14
  • 4. Fundamentals of XIL Drivers P2.mp4
    08:10
  • 5. Fundamentals of XIL Drivers P3.mp4
    03:36
  • 6. Working with MIO LED P1.mp4
    05:38
  • 7. Working with MIO LED P2.mp4
    16:15
  • 8. Code.html
  • 9. Working with GPIO MIO LED and Pushbutton P1.mp4
    04:16
  • 10. Working with GPIO MIO LED and Pushbutton P2.mp4
    05:16
  • 11. Code.html
  • 12. Working with EMIO LED P1.mp4
    05:31
  • 13. Working with EMIO LED P2.mp4
    11:44
  • 14. Code.html
  • 15. Single Channel AXI GPIO P1.mp4
    06:53
  • 16. Single Channel AXI GPIO P2.mp4
    11:48
  • 17. Code.html
  • 18. Dual Channel AXI GPIO P1.mp4
    02:56
  • 19. Dual Channel AXI GPIO P2.mp4
    07:18
  • 20. Code.html
  • 21. Failed to update xparameters.h P1.mp4
    01:32
  • 22. Failed to update xparameters.h P2.mp4
    07:44
  • 23.1 update_xparam.zip
  • 23. Code.html
  • 24. Multiple Instance of AXI GPIO P1.mp4
    04:24
  • 25. Multiple Instance of AXI GPIO P2.mp4
    08:12
  • 26. Code.html
  • 1. Working with MIO UART P1.mp4
    00:59
  • 2. Working with MIO UART P2 Changing Baud Rate Dynamically.mp4
    10:52
  • 3. Working with MIO UART P3 Sending Data.mp4
    06:50
  • 4. Working with MIO UART P4 Sending Data.mp4
    02:40
  • 5. Working with MIO UART P5 Receiving Data.mp4
    09:32
  • 6. Working with UARTLITE P1.mp4
    06:22
  • 7. Working with UARTLITE P2.mp4
    11:12
  • 1. Working with Private Watchdog (WDT) Timer P1.mp4
    04:09
  • 2. Working with Private Watchdog (WDT) Timer P2.mp4
    08:42
  • 3. Working with Private Watchdog (WDT) Timer P3.mp4
    08:36
  • 4. Code.html
  • 5. Working with Private 32-bit SCU Timer P1.mp4
    09:44
  • 6. Working with Private 32-bit SCU Timer P2.mp4
    07:35
  • 7. Code.html
  • 8. Understanding AUTO-RELOAD Mode P1.mp4
    07:12
  • 9. Understanding AUTO-RELOAD Mode P2.mp4
    11:55
  • 10. Code.html
  • 11. Using RESTART_TIMER for AUTO RELOAD Mode.mp4
    03:09
  • 12. Code.html
  • 13. Using Prescaler.mp4
    06:49
  • 14. Code.html
  • 15. Working with TTC P1.mp4
    04:05
  • 16. Working with TTC P2.mp4
    26:40
  • 17. Code.html
  • 18. Blinking effect on MIO LED with TTC P1.mp4
    01:37
  • 19. Blinking effect on MIO LED with TTC P2.mp4
    10:51
  • 20. Code.html
  • 21. Working with AXI Timer P1.mp4
    04:14
  • 22. Working with AXI Timer P2.mp4
    16:49
  • 23. Working with AXI Timer autoreload Mode P1.mp4
    03:47
  • 24. Working with AXI Timer autoreload Mode P2.mp4
    04:16
  • 25. Code.html
  • 26. Code.html
  • 27. Using Both Timers.mp4
    06:24
  • 28. Code.html
  • 29. Using AXI Timebase WDT P1.mp4
    04:05
  • 30. Using AXI Timebase WDT P2.mp4
    02:59
  • 31. Code.html
  • 1. Working with Serial Terminal P1.mp4
    01:51
  • 2. Working with Serial Terminal P2.mp4
    03:19
  • 3. Breakpoint P1.mp4
    04:55
  • 4. Breakpoint P2.mp4
    04:10
  • 5. Breakpoint P3.mp4
    07:23
  • 6. Working with Memory Viewer P1.mp4
    01:55
  • 7. Working with Memory Viewer P2.mp4
    02:55
  • 8. Working with Memory Viewer P3.mp4
    03:30
  • 1. Profiling with AXI Timer P1.mp4
    02:35
  • 2. Profiling with AXI Timer P2.mp4
    13:25
  • 3. Code.html
  • 4. Profiling with 64-bit Global Timer.mp4
    07:10
  • 5. Code.html
  • 6. Vitis Profiler P1.mp4
    03:13
  • 7. Vitis Profiler P2.mp4
    10:23
  • 8. Code.html
  • 1. Working with GPIO Interrupts P1.mp4
    04:46
  • 2. Working with GPIO Interrupts P2.mp4
    06:20
  • 3. Working with GPIO Interrupts P3.mp4
    09:11
  • 4. Working with GPIO Interrupts P4.mp4
    10:37
  • 5. Code.html
  • 6. Multiple Interrupts P1.mp4
    05:07
  • 7. Multiple Interrupts P2.mp4
    04:38
  • 8. Multiple Interrupts P3.mp4
    18:15
  • 9. Code.html
  • 10. Working with AXI Timer Interrupt P1.mp4
    02:22
  • 11. Working with AXI Timer Interrupt P2.mp4
    11:09
  • 12. Code.html
  • 13. Working with Private SCU Timer Interrupt P1.mp4
    03:34
  • 14. Working with Private SCU Timer Interrupt P2.mp4
    12:50
  • 15. Code.html
  • 16. Working with Private WDT Interrupt.mp4
    10:10
  • 17. Code.html
  • 18. Working with TTC Interrupt P1.mp4
    01:35
  • 19. Working with TTC Interrupt P2.mp4
    09:51
  • 20. Code.html
  • Description


    Using Xilinx Vivado Design Suite and Vitis 2020.2

    What You'll Learn?


    • Embedded System Design flow for Zynq AP SoC using Xilinx VITIS
    • Fundamentals strategies to use Xilinx Drivers
    • Development of C applications for Zynq Devices
    • Software Profiling with Vitis
    • Software and Hardware Debugging Strategies
    • Working with Interrupts

    Who is this for?


  • Anyone wish to build expertise in Xilinx Zynq APSOC and Xilinx VITIS Environment
  • Embedded System Design with FPGA Processors
  • What You Need to Know?


  • Understanding of Digital Electronics
  • Fundamentals of Computer Architecture
  • Fundamentals of C
  • More details


    Description

    Xilinx Zynq SoC's are know to provide maximum performance per watt along with maximum reconfiguration flexibility. Zynq family features Dual-Core ARM Cortex A9 processors tightly coupled with the 7-series FPGA to enable faster communication interfaces development with ARM Design flow and hardware acceleration. Zynq devices are available in two categories viz. Zynq-7000s family FPGA for the cost-effective application such as IoT related applications while Zynq 7000 family FPGA are best for high-performance applications such as Embedded Vision etc. The Zynq 7000s comes with Single core ARM while Zynq 7000 comes with Dual-Core ARM.

    This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of Hardware accelerators with Zynq based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Zynq to felicitate performance measurement.

    This course will create the foundation necessary to quickly start building applications on Zynq FPGA devices without prior experience in this domain.  The entire course is a Lab-based course with a major focussed on building skills necessary to handle simple peripherals such as GPIO, Intermediate Peripherals such as UART PS, AXI BRAM, and complex Peripherals such as AXI Interrupt Controller,  AXI Timers, GIC etc.

    Who this course is for:

    • Anyone wish to build expertise in Xilinx Zynq APSOC and Xilinx VITIS Environment
    • Embedded System Design with FPGA Processors

    User Reviews
    Rating
    0
    0
    0
    0
    0
    average 0
    Total votes0
    Focused display
    Kumar Khandagle
    Kumar Khandagle
    Instructor's Courses
    I am working as FPGA Developer Lead in India's Finest Financial Technology Firm for the development of a next-generation High-Frequency Trading platform on Xilinx Alveo FPGA Cards. Before Joining Fintech, I spent three years as a VLSI Trainer at Mumbai University, India, and one year as Research Scientist at the Prominent R&D Centre for Applied Electronic Research of India contributing to the development of  Gradient Controller,64 Mhz Receiver on FPGA for Indigenous MRI Machine. During my free time, I love to develop Udemy Courses. I also collaborated with Larsen & Toubro Technology Services, Power International in the development of various FPGA based Systems such as Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS. My area of interest includes Front End VLSI Design, SoC, and Chip Verification.
    Students take courses primarily to improve job-related skills.Some courses generate credit toward technical certification. Udemy has made a special effort to attract corporate trainers seeking to create coursework for employees of their company.
    • language english
    • Training sessions 82
    • duration 9:17:38
    • Release Date 2024/04/20