Digital Timing Basics for VLSI Interview & SoC Design

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1 - Introduction

1 - Introduction.mp4

05:36

2 - Understanding Flop Timings

2 - Basic Definitions.mp4

01:34

3 - Quick Summary.mp4

05:36

4 - Setup Time & Setup Margin.mp4

04:12

5 - Hold time & Hold Margin.mp4

03:33

6 - Clock to Q Delay.mp4

01:33

3 - Static Timing Foundation

7 - Buffer.mp4

03:47

8 - Logic Implementation.mp4

00:59

9 - Physical Implementation.mp4

06:03

10 - Setup Time Condition in Cycle Path.mp4

07:57

11 - Hold Time Condition in Cycle Path.mp4

08:00

12 - Example for Setup & Hold Condition.mp4

14:38

4 - Problem Solving for Interview

13 - Setup & Hold Margin Computation.mp4

06:03

14 - Setup Violation.mp4

05:10

15 - Setup Violation Fix Clock Path Delay.mp4

10:55

16 - Hold Violation.mp4

05:01

17 - Hold Violation Fix Data Path Delay.mp4

05:51

18 - Good Margin but Higher Latency.mp4

07:26

19 - Latency Reduction with Optimized Design.mp4

06:42

20 - Design Issues in Real World SoC.mp4

06:49

5 - Advanced Concepts for Interview Timing Margins

21 - Positive Latch Setup & Hold Time.mp4

12:08

22 - Negative Latch Setup & Hold Time.mp4

04:35

23 - Clock Gating Setup & Hold Time.mp4

10:10

24 - Negative Hold Time for Flop.mp4

10:45

25 - Negative Setup Time for Flop.mp4

08:03

6 - Common Misconceptions

26 - Setup Hold Clk2Q and Clock Skew.mp4

05:00

27 - Hold Margin with Frequency.mp4

03:27

28 - Setup Margin with Frequency.mp4

04:08

7 - Frequency vs Voltage in SoC

29 - FV Curve Introduction.mp4

06:37

30 - FV Curve Explanation.mp4

20:08

8 - Practical Design Issue1 Multiple Parallel Paths

31 - Multiple Path Problem Statement.mp4

01:42

32 - Multiple Path Setup Time Analysis.mp4

05:18

33 - Multiple Path Hold Time Analysis.mp4

05:28

34 - Multiple Path Summary.mp4

04:27

9 - Practical Design Issue 2 Max & Min Frequency of Operation

35 - Frequency of Operation.mp4

02:10

36 - Minimum Frequency of Operation.mp4

04:36

37 - Maximum Frequency of Operation without Clock Skew.mp4

02:42

38 - Maximum Frequency of Operation with Clock Skew.mp4

11:32

10 - Quiz & Next Step

39 - Next Step.mp4

00:31

Description

A VLSI Course on Timing Concepts frequently used in Physical Design (Static Timing Analysis - STA), RTL & Circuit Design

What You'll Learn?

Basics of Flop & Latch Timings
Set-up, Hold, Clock to Q, Clock Skew
Set-up & Hold violation checks
Set-up & Hold violation fixes
Latency Minimization
Set-up & Hold Margin in Digital Ckts
Min & Max Path Analysis
Clock Gating
F-V Curve in SoC

Who is this for?

VLSI students

VLSI professionals

Electronics Engineer

Electrical Engineer

Physical Design Engineer

RTL Designer

Circuit Designer

Verification Engineer

SoC Designer

More details

Description
AÂ VLSIÂ Course on Basic Timing Checks for Digital Logics - AÂ MUSTÂ Course for VLSIÂ students and professionals intended to work in Physical Design / Front-end (RTL)Â Design / Verification / Circuit Design.
Understanding of Flop, Latch and Logic Gates timings (Set-up time, hold-time, Clock to Q delay) is very crucial for every VLSI designer. Whether you are working as Physical Designer (back-end) or RTL designer (front-end) or Verification engineer or Circuit Designer, Digital logics and associated timings form the basis of design performance in SoC design.
Clock skew is another important factor in Static Timing Analysis. This course will cover most critical timing aspects of Flops and how set-up and hold margins are computed in Digital design. In addition, this course will provide insights to latency minimization, another crucial aspect of Physical Design.
This is a MUSTÂ Course for every VLSIÂ aspirants who aspire for a successful career in semiconductor industry. If you are preparing for VLSIÂ interview or GATEÂ exam, then this is right course for you.
All the concepts taught in this lecture series are followed by relevant examples which will help students to get a full understanding of each concept. This is perfect course for VLSIÂ interview preparation.
This Crash Course is prepared by VLSIÂ industry expert with inputs from Industry professionals working in companies such as Texas Instruments, AMD, Intel, Qualcomm, Rambus, Samsung etc.
Concepts covered in this course are - Flop and Latch operation, Set-up time, Hold time, Clock to Q delay, Buffer, Clock Skew, Set-up Margin, Hold Margin, Cycle path analysis, Digital vs Physical implementation, Example of violations and fixing those violations, Latency minimization, Clock-Gating and Frequency-Voltage Curve in SoC.
All the best for your VLSIÂ journey!
Who this course is for:
VLSI students
VLSI professionals
Electronics Engineer
Electrical Engineer
Physical Design Engineer
RTL Designer
Circuit Designer
Verification Engineer
SoC Designer

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