Building Processor with VHDL from Scratch

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Kumar Khandagle

2:52:07

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1. Adding Arithmetic Unit

1. Understanding Processor architecture.mp4

04:37

2. Agenda.mp4

00:54

3. Types of Instructions.mp4

08:41

4. Addressing Modes.mp4

04:35

5. Understanding Intruction Register.mp4

03:48

6. Creating new project in Vivado.mp4

03:53

7. Adding MOV instruction to processor P1.mp4

05:16

8. Adding MOV instruction to processor P2.mp4

05:26

9. Verifying RTL Designing.mp4

05:06

10. Design Code.html

11. Testbench Code.html

12. Adding Arithmetic Instructions to Processor.mp4

06:46

13. Verifying Design.mp4

02:44

14. Design Code.html

15. Testbench Code.html

16. A11 Testing Multiplication operation.html

2. Adding Logic Unit

1. Agenda.mp4

00:52

2. Logical Operators in VHDL.mp4

03:09

3. Adding Logical Unit to Processor.mp4

02:17

4. Testing Logical Operation.mp4

04:42

5. Design Code.html

6. Testbech Code.html

7. Understanding Subprogram in VHDL.mp4

02:19

8. Working with Procedure.mp4

07:05

9. Code.html

10. Converting Instruction Decoder to Procedure.mp4

06:17

11. Design Code.html

12. Testbench Code.html

13. A21 Testing Logical Operation in Register mode.html

3. Adding Condition Flags

1. Agenda.mp4

01:02

2. Condition flags usage.mp4

01:24

3. Understanding Carry Flag.mp4

02:42

4. Understanding Overflow flag.mp4

06:20

5. Understanding Sign and Zero Flag.mp4

03:33

6. Adding Condition flags to processor.mp4

08:31

7. Testing Operation of Condition flags.mp4

04:38

8. Design Code.html

9. Testbench Code.html

4. Adding Program and Data Memory to Processor

1. Agenda.mp4

01:04

2. Processor architecture based on Memory model.mp4

03:07

3. Testbench Code.html

4. Adding Program Memory to processor P1.mp4

07:56

5. Adding Program Memory to processor P2.mp4

01:37

6. Program Data.html

7. Design Code.html

8. Testbench Code.html

9. Adding Control FSM to processor P1.mp4

08:57

10. Adding Control FSM to processor P2.mp4

03:00

11. Program Data.html

12. Design Code.html

13. Testbench Code.html

14. Working with Data Memory and IO Ports P1.mp4

05:34

15. Working with Data Memory and IO Ports P2.mp4

03:46

16. Program Data.html

17. Design Code.html

18. Testbench Code.html

5. Adding Jump and Branch Instructions

1. Agenda.mp4

00:40

2. Branch and Jump Instructions our processor support.mp4

03:08

3. Operation of Jump Instructions.mp4

01:56

4. FSM to handle Jump and Halt P2.mp4

05:20

5. Testing Previous Code.mp4

05:20

6. Program Data.html

7. FSM to handle Jump and Halt P1.mp4

06:50

8. Design Code.html

9. Testbench Code.html

10. Testing Jump Instruction.mp4

01:21

11. Program Data.html

12. Design Code.html

13. Testbench Code.html

14. Testing Halt Instruction.mp4

01:54

15. Program Data.html

16. Testing Branch Instructions.mp4

04:00

17. Program Data.html

18. Design Code.html

19. Testbench Code.html

Description

Step by Step Guide

What You'll Learn?

Startegies to implement VHDL based CPU
Buliding Custom Intruction Set to meet resource utilizations
Strategies to add Program and Data Memory inside Processor
Strategies to add Jump and Branching Instructions inside Processor

Who is this for?

Anyone Interested to build Custom CPU on FPGA for Load Sharing

What You Need to Know?

Fundamentals of Digital Electronics

More details

Description
Most of the 21st-century applications require powerful hardware but also along with the centralized controller allowing the development of complex algorithms. As we enter into the AI or Cloud-based devices and as systems complexity is growing daily, the need for incorporating multiple processor instances becomes mandatory as we progress in the AI era. Zynq and Microblaze are two popular alternatives that exist in the market suitable for almost any application requirements. The requirements of using Multiple instances of Processor viz. Multiple instances of Microblaze soft processor or using a hard processor such as Zynq Processor along with single or multiple instances ofÂ Microblazer become necessary to independently handle both Data processing and control requirements. The fundamental challenge of incorporating multiple instances of Soft processors like Microblaze is the number of resources consumed for implementing Microblaze on the FPGA. Since FPGA consists of a limited amount of the FPGA resources, hardware and Software partition plays a prominent role in building complex systems. Another popular alternative approach followed by Embedded Engineers to build a Custom CPU /Â Â Processor with the only required functionality thereby saving a large amount of the resources as compared to adding Microblaze instance. The course will discuss all the fundamentals required to build a simple processor/ CPU with VHDL and strategies to test its functionality. After completing this course, you will understand all the necessary skills required to build Complex CPU architecture to meet requirements. Best wishes for crafting your own processor.
Who this course is for:
Anyone Interested to build Custom CPU on FPGA for Load Sharing

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I am working as FPGA Developer Lead in India's Finest Financial Technology Firm for the development of a next-generation High-Frequency Trading platform on Xilinx Alveo FPGA Cards. Before Joining Fintech, I spent three years as a VLSI Trainer at Mumbai University, India, and one year as Research Scientist at the Prominent R&D Centre for Applied Electronic Research of India contributing to the development of Gradient Controller,64 Mhz Receiver on FPGA for Indigenous MRI Machine. During my free time, I love to develop Udemy Courses. I also collaborated with Larsen & Toubro Technology Services, Power International in the development of various FPGA based Systems such as Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS. My area of interest includes Front End VLSI Design, SoC, and Chip Verification.

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