Building a Processor with Verilog HDL from Scratch

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Kumar Khandagle

2:36:44

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1. Adding Arithmetic Unit

1. Types of Instructions.mp4

08:41

2. Addressing Modes.mp4

04:35

3. Understanding Intruction Register.mp4

03:48

4. Adding Instruction Register and GPR to Processor.mp4

04:35

5. Understanding Arithmetic and Move intructions of Processor.mp4

04:59

6. Adding MOV Instructions.mp4

03:57

7. Adding Arithmetic Instructions.mp4

03:48

8. Adding TB to verify Instructions P1.mp4

09:05

9. Adding TB to verify Instructions P2.mp4

01:02

2. Adding Logical Unit

1. Supported Logical Operations.mp4

02:47

2. Adding Logical operations to RTL.mp4

02:48

3. Adding TB to verify Logical Operations.mp4

02:28

4. Analyzing RTL output.mp4

01:07

3. Adding Conditions Flags

1. Condition flags usage.mp4

01:24

2. Logic for Carry, Sign, and Zero Flag.mp4

03:39

3. Logic for Overflow flag.mp4

08:08

4. Adding Carry, Sign, and Zero flag to RTL.mp4

04:07

5. Adding Overflow flag to RTL.mp4

02:32

6. Verifying operation of condition flags.mp4

03:38

4. Adding Program and Data memory

1. Processor architecture based on Memory model.mp4

03:07

2. Working with Memory Generator IP.mp4

13:41

3. Working with Verilog arrays.mp4

07:09

4. Adding Memory to Processor RTL P1.mp4

02:12

5. Converting independent always block to tasks.mp4

01:13

6. Adding logic to read Instructions from Program Memory after fixed delay.mp4

04:10

7. Adding Instructions to work with Ports and Data Memory.mp4

04:48

8. Program use for testing operation of RTL.mp4

07:28

9. Adding TB to verify operation of RTL.mp4

05:19

5. Adding Jumping and Branching Instructions

1. Branch and Jump Instructions our processor support.mp4

03:08

2. Operation of Jump Instructions.mp4

01:56

3. Adding Jump instructions to Processor RTL.mp4

05:42

4. Modifying FSM to incorporate Jump, Branch and Halt Flowchart.mp4

02:46

5. Adding FSM to RTL.mp4

08:26

6. Testing existing program with new FSM.mp4

02:42

7. Code to Verify Jump and Branch Instructions.mp4

04:28

8. Executing Testbench Code.mp4

01:21

Description

Using Xilinx Vivado 2020.2

What You'll Learn?

Startegies to implement Verilog based CPU
Buliding Custom Intruction Set to meet resource utilizations
Strategies to add Program and Data Memory inside Processor
Strategies to add Jump and Branching Instructions inside Processor

Who is this for?

Anyone Interested to build Custom CPU on FPGA for Load Sharing

More details

Description
Most of the 21st-century applications require powerful hardware but also along with the centralized controller allowing the development of complex algorithms. As we enter into the AI or Cloud-based devices and as systems complexity is growing daily, the need for incorporating multiple processor instances becomes mandatory as we progress in the AI era. Zynq and Microblaze are two popular alternatives that exist in the market suitable for almost any application requirements. The requirements of using Multiple instances of Processor viz. Multiple instances of Microblaze soft processor or using a hard processor such as Zynq Processor along with single or multiple instances ofÂ Microblazer become necessary to independently handle both Data processing and control requirements. The fundamental challenge of incorporating multiple instances of Soft processors like Microblaze is the number of resources consumed for implementing Microblaze on the FPGA. Since FPGA consists of a limited amount of the FPGA resources, hardware and Software partition plays a prominent role in building complex systems. Another popular alternative approach followed by Embedded Engineers to build a Custom CPU /Â Â Processor with the only required functionality thereby saving a large amount of the resources as compared to adding Microblaze instance. The course will discuss all the fundamentals required to build a simple processor/ CPU with Verilog HDL and strategies to test its functionality. After completing this course, you will understand all the necessary skills required to build Complex CPU architecture to meet requirements. Best wishes for crafting your own processor.
Who this course is for:
Anyone Interested to build Custom CPU on FPGA for Load Sharing

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Verilog HDL Programming

Kumar Khandagle

Instructor's Courses

I am working as FPGA Developer Lead in India's Finest Financial Technology Firm for the development of a next-generation High-Frequency Trading platform on Xilinx Alveo FPGA Cards. Before Joining Fintech, I spent three years as a VLSI Trainer at Mumbai University, India, and one year as Research Scientist at the Prominent R&D Centre for Applied Electronic Research of India contributing to the development of Gradient Controller,64 Mhz Receiver on FPGA for Indigenous MRI Machine. During my free time, I love to develop Udemy Courses. I also collaborated with Larsen & Toubro Technology Services, Power International in the development of various FPGA based Systems such as Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS. My area of interest includes Front End VLSI Design, SoC, and Chip Verification.

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