Joel S. Emer

Joel S. Emer is a Senior Distinguished Research Scientist with Nvidia's Architecture Research Group and a Professor of the Practice at MIT. His research has focused on various aspects of computer architecture, where he has been acknowledged as one of the developers of the widely employed quantitative approach to processor performance evaluation. He been also been recognized for his pioneering research contributions in the advancement of simultaneous multithreading technology, processor reliability analysis, cache organization, pipelined processor organization and spatial architectures for deep learning. He has also made architectural contributions to a number of VAX, Alpha, and X86 processors. He has received a number awards including the Eckert-Mauchly Award for lifetime contributions in computer architecture, the Purdue University Outstanding Electrical and Computer Engineer Alumni Award and the University of Illinois Electrical and Computer Engineering Distinguished Alumni Award. His paper on simultaneous multithreading received the ACM/SIGARCH-IEEE-CS/TCCA Most Influential Paper Award, and six other papers have been selected as IEEE Micro's Top Picks in Computer Architecture. He is a Fellow of the ACM and IEEE and a member of the NAE.